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ZXLD1100
ELECTRICAL CHARACTERISTICS (at V IN = 3V , T amb = 25°C unless otherwise stated (1) )
SYMBOL
V IN
PARAMETER
Input voltage
CONDITIONS
MIN.
2.5
TYP.
MAX. UNIT
5.5
V
I IN
Supply current
Quiescent
Shutdown
V EN = V IN , I LX = 0,
Output not switching
V EN = 0V
60
100
500
A
nA
V FB
I FB
FB pin control voltage
FB pin input current
90.5
109.5
100
mV
nA
f LX
T OFF
T ON
I LXpk
Operating frequency
LX output 'OFF' time
LX output 'ON' time (2)
Switch peak current limit
L=10 H, V OUT =10V,
I OUT =20mA
L=10 H, V OUT =10V,
I OUT =20mA
350
0.35
500
320
1
5
MHz
ns
μs
mA
R LX
Switch 'On' resistance
1.5
I LX(leak)
V OUT
Switch leakage current
Controller output voltage
V LX =20V
Normal operation
VSENSE pin
1
28
μA
V
open-circuit or
grounded
V OUT(MAX) Controller output voltage with output
open circuit (3)
VSENSE connected to
Vout
25
30
V
V ENH
V ENL
I ENL
I ENH
EN pin High level Input voltage
EN pin Low level Input voltage
EN pin Low level input current
EN pin High level input current
Device active
Device in shutdown
V EN =0V
V EN =V IN
1.5
V IN
0.4
-100
1
V
V
nA
A
T EN(hold)
EN pin turn off delay
(4)
V EN switched from
high to low
120
μs
? T/T
f LPF
A LPF
PWM duty cycle range at ‘EN ’ input for
filtered PWM control (5)
Internal PWM low pass filter cut-off
frequency
Filter attenuation
10kHz < f < 100kHz,
V ENH =V IN
f=30kHz
20
4
52.5
100
%
kHz
dB
NOTES:
(1) Production testing of the device is performed at 25°C. Functional operation of the device over a -40°C to +85°C temperature range is
guaranteed by design, characterization and process control.
(2) Nominal 'on' time (T ONnom ) is defined by the input voltage (V IN ), coil inductance (L) and peak current (I LXpkdc ) according to the expression:
T ONnom = {I LX(pkdc ) x L/V IN } +200ns.
(3) When using the open circuit protection feature, the maximum output voltage under normal operation should be maintained below the
minimum value specified, in order to prevent possible disturbance of the current control loop.
(4) This is the time for which the device remains active after the EN pin has been asserted low. This delay is necessary to allow the output to be
maintained during dc PWM mode operation.
(5) The minimum PWM signal frequency during this mode of operation is to ensure that the device remains active during PWM control. This
provides a continuous dc output current. For lower frequencies, the device will be gated 'on' and 'off' during PWM control.
(6) The maximum PWM signal frequency during this mode of operation should be kept as low as possible to minimize errors due to the turn-off
delay of the device (see Enable pin turn-off delay).
ISSUE 4 - JULY 2004
3
SEMICONDUCTORS
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